Flash memory is a commonly used type of non-volatile memory in widespread use as mass storage for consumer electronics, such as digital cameras and portable digital music players for example. The density of a presently available flash memory chip can be up to several Gbytes (GB) in size, which is suitable for use in popular USB flash drives since the size of one flash chip is small. Another emerging application for flash memory are solid state drives for replacing traditional hard disk drives used in laptop and desktop computers.
FIG. 1 is a general block diagram of typical flash memory device known in the art. Flash memory device 10 includes input/output interface circuits, control circuits, memory circuits and a memory array. The input/output interface circuits of flash memory device 10 include a Ready/Busy signal buffer 12, control signal buffers 14 and global data buffers 16. The Ready/Busy signal buffer 12 is an output buffer which drives the Ready/Busy signal R/B# via a respective pin or port. In the present example, the control signal buffers 14 are input buffers which receive flash memory control signals CE#, CLE, ALE, WE#, RE# and WP# from corresponding pins or ports. Signal names ending with “#” should be understood from this point forward as being active low level signals, where an active low signal corresponds to a “0” logic level, or a VSS voltage level for example. In contrast, an active high logic level signal corresponds to a “1” logic level, or a VDD or VCC voltage level for example. Following is a short description of the previously mentioned control signals.                Command Latch Enable (CLE): the CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE# signal while CLE is High.        Address Latch Enable (ALE): the ALE signal is used to control loading address information into the internal address register. Address information is latched into the address register from the I/O port on the rising edge of the WE# signal while ALE is High.        Chip Enable (CE#): the device goes into a low-power Standby mode when CE# goes High during the device is in Ready state. The CE# signal is ignored when device is in Busy state (R/B#=L), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE# input goes High.        Write Enable (WE#): the WE# signal is used to control the acquisition of data from the I/O port.        Read Enable (RE#): the RE signal controls serial data output. Data is available after the falling edge of RE#. The internal column address counter is also incremented (Address=Address+I) on this falling edge.        I/O Port (I/O0 to 7): I/O0 to 7 pins are used as a port for transferring address, command and input/output data to and from the device.        Write Protect (WP#): the WP# signal is used to protect the device from accidental programming or erasing. The internal voltage regulator (high voltage generator) is reset when WP# is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid.        Ready/Busy (R/B#): the R/B# is open drain pin and the output signal is used to indicate the operating condition of the device. The R/B# signal is in Busy state (R/B#=L) during the Program, Erase and Read operations and will return to Ready state (R/B#=H) after completion of the operation.        
The global data buffers 16 in the present example of FIG. 1 are bi-directional buffers which receive write data and provide read data on respective input/output (I/O) pins or ports. The flash memory device 10 is shown to have 8 such ports I/O0 to I/O7, but can have more or less than 8 in alternate data width configurations. These I/O ports are also used for receive address and command information.
The control circuits of flash memory device 10 include controller 18, command register 20, address register 22 and status register 24. Controller 18 controls various functions of the other circuits in flash memory device 10, where such functions include read, program and program verification. While not shown, the controller 18 can include a command decoder for executing the functions in response to a received command. The registers store types of information received by flash memory device 10 or to be provided to an external host system, including a memory controller for example. The described registers are not intended to be exhaustive, and other registers can be included, such as data registers for example.
The circuits primary controlled by controller are the memory circuits, which include row and column pre-decoders 26 and 28, row and column decoders 30 and 32, sense amplifiers and page buffer block 34, and a high voltage generator 36. The memory array 38 of flash memory device 10 consists of NAND cell strings connected to bitlines, where each memory cell of a NAND cell string is connected to a wordline. Further details of a NAND cell string is shown later in FIG. 3. The row pre-decoder 26, row decoder 30 and high voltage generator 36 are controlled in a programming operation to drive a selected wordline to a high voltage effective for shifting a threshold voltage of the connected memory cell from a default erased threshold voltage to a desired voltage level. It is noted that a high voltage may be used in the memory array 38 to erase memory cells by shifting their threshold voltages to the default value. Different combinations of high voltages and applied time of the high voltages can be used to set specific threshold voltages for a flash memory cell. A combination for programming a specific threshold voltage can be referred to as a programming profile. The page buffer 34 stores a page of data to be programmed to the cells connected to the selected wordline. Generally, a memory cell connected to a bitline is either inhibited from being programmed or enabled for programming via the selected wordline, depending on the logic level the bitline is biased, or set to. The data bits stored in the page buffer are used to bias the bitline.
FIG. 2 is a threshold voltage distribution graph for a single bit flash memory cell, which stores one of two possible levels or states, State 0 or State 1. This is also referred to as single level cell (SLC) memory. In FIG. 2, State 0 is the default erased state of all flash memory cells of memory array 38, which in this example is a negative threshold voltage. In contrast, State 1 corresponds to a positive threshold voltage. Therefore when erased, the flash memory cells stores the “1” logic state for a single bit of stored data. Programming is then executed to shift the erased threshold voltage to the positive voltage of State 1 if the data to be stored in a selected cell corresponds to a “0”, which as previously explained is done by driving the selected wordline connected to the cell with a particular programming profile.
FIG. 3 is a circuit schematic showing a portion of memory array 38 of FIG. 1, and in particular shows NAND cell strings connected to two bitlines BL1 and BLj. Each NAND cell string has flash memory cells 50 serially coupled arranged and electrically coupled to each other. Accordingly, wordlines WL0 to WLi are coupled to the gates of each flash memory cell 50 in the memory cell string. Place holders “i” and “j” are integer values, designating a last wordline and bitline respectively. A string select device 52 coupled to signal SSL (string select line) selectively connects the memory cell string to a bitline (BL1 or BLj), while a ground select device 54 coupled to signal GSL (ground select line) selectively connects the memory cell string to a source line, such as VSS. The string select device 52 and the ground select device 54 are n-channel transistors. The two NAND cell strings shown in FIG. 3 connected to the same wordlines, SSL and GSL are part of one memory block 56. Accordingly, there can be multiple memory blocks connected to the same bitlines BL1 to BLj in parallel to the memory block shown in FIG. 1.
If flash memory cells 50 store a single bit of data, then all the cells 50 connected to the same wordline store a page of data. In FIG. 3 by example, the cells connected to WL0 are collectively referred to physical Page 0, while the cells connected to WLj are collectively referred to as physical Page i, where each stores one page of data.
Coupled to each bitline BL1 to BLj is a page buffer 58 for storing one page of data to be programmed into one page of flash memory cells. Page buffer 58 also includes sense circuits for sensing data read from one page of flash memory cells. During programming operations, the data registers perform program verify operations to ensure that the data has been properly programmed into the flash memory cells coupled to the selected wordline. Therefore, each row of cells stores a page of data. To achieve improved density, each flash memory cell can store at least two bits of data, and is generally referred to as a multi-bit-cell (MBC). In storing at least two bits of data per cell, the storage density of a memory array is at least doubled relative to the same memory array having cells that store only one bit of data.
FIG. 4 is a threshold voltage distribution graph for a two-bit flash memory cell. This is also referred to as multiple level per cell (MLC) memory. FIG. 4 shows four possible states, State 0, State 1, State 2 and State 3, which can be stored by a two-bit flash memory cell. As shown by example in FIG. 4, each state corresponds to a combination of two bits of data. State 0 can represent binary values “11”, State 1 can represent binary values “10”, State 2 can represent binary values “00”, and State 3 can represent binary values “01”. The binary values shown in FIG. 4 are example combinations, and the assignment of binary value combinations for each state can differ from those presently shown in FIG. 4. Accordingly, a row of flash memory cells connected to the same wordline can now store two pages of data, instead of the single page of data for the single bit flash memory cell. The logical organization of these two pages of data, referred to as logical pages, associated with cells connected to a common wordline, referred to as a physical page, is now described.
FIG. 5 is an illustration showing storage of lower and upper pages of data stored in rows of two-bit flash memory cells. In FIG. 5, flash memory cells 70 and 72 are part of a first NAND cell string, flash memory cells 74 and 76 are part of a second NAND cell string, flash memory cells 78 and 80 are part a last NAND cell string, representing the last NAND cell string in a memory block. Depending on the configuration of the block, there can be a plurality of intervening NAND cell strings between the second NAND cell string and the last NAND cell string. Each of the flash memory cells has one of the four possible logic states shown in FIG. 4, with the corresponding two-bit binary value assignments. In the example of FIG. 5, cell 70 stores State 3, cell 72 stores State 1, cell 74 stores State 1, cell 76 stores State 3, cell 78 stores State 2, and cell 80 stores State 0. The binary values are shown in each cell, where the upper bit corresponds to the left-most bit in the corresponding state of FIG. 4 and the lower bit corresponds to the right-most bit. The flash memory cells 72, 76 and 80 connected to wordline WL0 correspond to a physical page having lower bits of flash memory cells 72, 76 and 80 correspond to logical page 0, while the upper bits correspond to logical page 1. Similarly, the flash memory cells 70, 74 and 78 connected to wordline WLi correspond to another physical page having lower bits corresponding to logical page k−1, while the upper bits correspond to a last logical page k. Therefore, it can be seen how each physical page stores two pages of data.
By extension, if each flash memory cell can store 3 bits of data, then each cell can store 23=8 states, which means that each physical page can store up to 8 pages of data. Provided all the different states can be programmed and sensed during a read operation, the increase in storage density without the need for increasing the physical memory array size affords significant advantages for mass storage applications. Unfortunately, the time required for programming two pages of data (two bits per cell) per physical page is significantly increased relative to programming a single page of data per physical page. This increased programming time is further exacerbated if 3 or more bits per cell storage is used.
While the time required for occasionally copying several small data files to a USB drive capable of multiple bit per cell storage may not appear inconvenient for users, the frequent writing of a large number of small data files will noticeably take a longer amount of time. Frequent writing of smaller data files is common in solid state hard disk drives, which can impose a performance limitation on the computer system it is used within. Storage of larger data files such as music and video files to flash memory capable of storing multiple bits per cell will take a very noticeable duration of time to program.
As flash memories are widely used in computing applications such as Sods and flash cache, higher performance flash memories are desired. It should be noted that high performance operation can be obtained with one or more of higher I/O bandwidth, higher read and write throughput and higher flexibility of operations. Moreover flash storage systems for computing applications require higher memory capacity without diminishing performance.
It is therefore desirable to reduce the time required for programming cells storing two or bits of data, to thereby improve overall performance of the system it is used within.